Semiconductor device

ABSTRACT

A first wiring layer overlying a semiconductor substrate has the arrangement of adjacent wirings in the order of first wirings and first shield wirings. A second wiring layer overlying the semiconductor substrate has the arrangement of adjacent wirings in the order of second shield wirings and second wirings to correspond to the respective first wirings and first shield wirings in the first wiring layer. Thus, the capacitance between adjacent wirings is reduced as well as the noise between adjacent wirings. Further, power consumption is reduced without a decrease in the action speed of a signal.

TECHNICAL FIELD

The present invention relates to a wiring structure of a semiconductordevice.

BACKGROUND ART

As the designs of semiconductor devices become finer, a capacitancebetween wirings has become a problem on circuit designs. Particularly, acapacitance between adjacent wirings delays the driving time of signallines.

Referring to FIG. 28, an example of a conventional wiring structure willbe briefly described. FIG. 28 shows an example of wiring only using asingle wiring layer. The wiring layer has a tight arrangement. In thisway, as a wiring layer making contact with the source or drain of adevice such as a transistor, the lowest wiring layer is generally used,and the minimum wiring is frequently provided according to a pitch ofcontact.

However, the conventional semiconductor device increases a capacitancebetween adjacent wirings and increases noise between adjacent wirings,lowering the operating speed of signals.

Further, as a capacitance between wirings becomes larger, powerconsumption also increases.

Moreover, when the wiring structure is used for a bit line of a memory,it is difficult to read a necessary potential from a memory cell to thebit line.

Additionally, in reverse, in the case of memory such as a ferroelectricmemory or the like requiring a suitable wiring capacitance, it isdifficult to reduce noise between adjacent wirings and set a suitablewiring capacitance at the same time.

Under the circumstances, an object of the present invention is toprovide a semiconductor device which can reduce a capacitance betweenadjacent wirings, noise between adjacent wirings, and power consumptionwithout lowering the operating speed of a signal.

DISCLOSURE OF INVENTION

A semiconductor device according to the present invention has thefollowing wiring structure.

Wirings are formed in a plurality of wiring layers and a distance isincreased between the wiring layers to reduce noise between the wiringlayers. First, a capacitance between wirings between the layers isreduced, and wirings in a first wiring layer and a second wiring layerare arranged on different positions taken from the top, so that acapacitance between wirings can be reduced between the first wiringlayer and second wiring layer.

Moreover, the following wiring structure is provided: a first wiring, afirst shield wiring, and a second wiring are arranged in this order inthe first wiring layer, and a third wiring, a second shield wiring, anda fourth wiring are arranged in this order in the second wiring layer.

Besides, the first shield wiring and the second shield wiring are groundvoltage lines or power voltage lines. Further, the ground voltage linesand the power voltage lines are alternately arranged, or the firstwiring layer is used as a ground voltage line and the second wiringlayer is used as a power voltage line.

Moreover, the arrangement has two wiring layer regions and the wiringsof the wiring layer regions are connected to each other, so that thewiring structure can offer a preferred balance of a resistance and acapacitance.

Moreover, the shield wiring is larger in width than the signal wiring inthe wiring structure.

Besides, the lowest wiring layer is constituted of a single wiring layeras with the conventional art. An upper layer thereon has a wiringstructure of a first wiring, a first shield wiring, and a second wiringthat are arranged in this order. An upper layer thereon has a wiringstructure of a third wiring, a second shield wiring, and a fourth wiringthat are arranged in this order.

According to these arrangements of the semiconductor device, it ispossible to reduce a capacitance between adjacent wirings, noise betweenadjacent wirings, and power consumption without lowering the operatingspeed of a signal.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a top view showing a semiconductor device according toEmbodiment 1 of the present invention;

FIG. 2 is a sectional view showing the semiconductor device according toEmbodiment 1 of the present invention;

FIG. 3 is a top view showing a semiconductor device according toEmbodiment 2 of the present invention;

FIG. 4 is a sectional view showing the semiconductor device according toEmbodiment 2 of the present invention;

FIG. 5 is a top view showing a semiconductor device according toEmbodiment 3 of the present invention;

FIG. 6 is a top view showing a semiconductor device according toEmbodiment 4 of the present invention;

FIG. 7 is a top view showing a semiconductor device according toEmbodiment 5 of the present invention;

FIG. 8 is a top view showing a semiconductor device according toEmbodiment 6 of the present invention;

FIG. 9 is a top view showing a semiconductor device according toEmbodiment 7 of the present invention;

FIG. 10 is a top view showing a semiconductor device according toEmbodiment 8 of the present invention;

FIG. 11 is a top view showing a semiconductor device according toEmbodiment 9 of the present invention;

FIG. 12 is a sectional view showing the semiconductor device accordingto Embodiment 9 of the present invention;

FIG. 13 is a top view showing a semiconductor device according toEmbodiment 10 of the present invention;

FIG. 14 is a sectional view showing the semiconductor device accordingto Embodiment 10 of the present invention;

FIG. 15 is a top view showing a semiconductor device according toEmbodiment 11 of the present invention;

FIG. 16 is a sectional view showing the semiconductor device accordingto Embodiment 11 of the present invention;

FIG. 17 is a top view showing a semiconductor device according toEmbodiment 12 of the present invention;

FIG. 18 is a sectional view showing the semiconductor device accordingto Embodiment 12 of the present invention;

FIG. 19 is a sectional view showing the semiconductor device accordingto Embodiment 12 of the present invention;

FIG. 20 is a top view showing a semiconductor device according toEmbodiment 13 of the present invention;

FIG. 21 is a sectional view showing the semiconductor device accordingto Embodiment 13 of the present invention;

FIG. 22 is a top view showing a semiconductor device according toEmbodiment 14 of the present invention;

FIG. 23 is a sectional view showing the semiconductor device accordingto Embodiment 14 of the present invention;

FIG. 24 is a sectional view showing a semiconductor device according toEmbodiment 15 of the present invention;

FIG. 25 is a sectional view showing a semiconductor device according toEmbodiment 16 of the present invention;

FIG. 26 is a top view showing a semiconductor device according toEmbodiment 17 of the present invention;

FIG. 27 is a sectional view showing the semiconductor device accordingto Embodiment 17 of the present invention; and

FIG. 28 is a sectional view showing a conventional semiconductor device.

BEST MODE FOR CARRYING OUT THE INVENTION

With reference to the accompanying drawings, a semiconductor deviceaccording to embodiments of the present invention will be specificallydescribed below.

EMBODIMENT 1

Embodiment 1 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 1 is a top view of Embodiment 1, andFIG. 2 is a sectional view taken along line A1-A2 of FIG. 1.

First, wirings (e.g., signal lines) M12, M14, M16, and M18 are arrangedin this order in a first wiring layer. Then, on the first wiring layer,signal lines M21, M23, M25, and M27 are arranged in this order in asecond wiring layer. In this case, the signal lines in the first wiringlayer and the second wiring layer are arranged at almost equalintervals. Further, the signal lines M21 and M12, the signal lines M23and M14, the signal lines M25 and M16, and the signal lines M27 and M18are connected to amplifiers. In the present embodiment, the signal linesM12, M14, M16, and M18 and the signal lines M21, M23, M25, and M27 arearranged on different positions taken from the top. As compared with thecase where the signal lines are arranged on the same positions takenfrom the top, noise can be reduced between the signal lines.

Embodiment 1 has the following effect: the signal lines are arrangedusing the two wiring layers and shield wirings are placed between thesignal lines, so that it is possible to reduce a capacitance betweenadjacent wirings, noise between adjacent wirings, and power consumptionwithout reducing the operating speed of a signal. Particularly, sincethe signal lines of the first wiring layer and the second wiring layerare arranged on different positions taken from the top, a great effectcan be achieved.

EMBODIMENT 2

Embodiment 2 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 3 is a top view of Embodiment 2, andFIG. 4 is a sectional view taken along line A1-A2 of FIG. 3.

Unlike Embodiment 1, a first wiring layer and a second wiring layer haveadjacent signal lines in pairs in the present embodiment. Wirings arenot arranged at equal intervals in each of the wiring layers. Further,the signals of the adjacent wirings are connected to amplifiers.

Embodiment 2 has the following effect: signal lines are arranged usingtwo wiring layers as with Embodiment 1, so that it is possible to reducea capacitance between adjacent wirings, noise between adjacent wirings,and power consumption without reducing the operating speed of a signal.Particularly since the signal lines of the first wiring layer the secondwiring layer are arranged on different positions taken from the top, agreat effect can be achieved.

Additionally, since the wirings connected to the same amplifier arearranged in the same layer, it is possible to reduce the influence ofvariations or the like during the manufacturing of the wirings.

EMBODIMENT 3

Embodiment 3 the present invention will be discussed below according tothe accompanying drawings. FIG. 5 is a top view of Embodiment 3.

Unlike Embodiment 1, electrically connected wirings are transferred toand from a first wiring layer and a second wiring layer at some midpointin the present embodiment. Since this structure has both regions of thefirst wiring layer and the second wiring layer, the same arrangement isprovided over the wirings.

With this arrangement, it is possible to reduce the influence ofvariations or the like during the manufacturing of the wiring.

Further, the electrically connected wirings on signals are arrangedalmost like a straight line taken from the top. The connecting part ofthe wirings in the first wiring layer and the second wiring layer do notintersect the other wirings, achieving a simple layout. The connectionconfiguration of amplifiers is the same as Embodiment 1.

EMBODIMENT 4

Embodiment 4 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 6 is a top view of Embodiment 4.

Unlike Embodiment 1, electrically connected wirings are transferred toand from a first wiring layer and a second wiring layer at some midpointin the present embodiment. Since this structure has both regions of thefirst wiring layer and the second wiring layer, so that the samearrangement is provided over the wirings.

With this arrangement, it is possible to reduce the influence ofvariations or the like during the manufacturing of the wirings.

Further, taken from the top, the electrically connected wirings onsignals are not arranged almost like a straight line taken from the topbut the wirings in the same wiring layer are arranged almost like astraight line. For example, when another wiring layer is provided on thesecond wiring in the same direction, almost equal noise is set for apair of wirings connected to the same amplifier, thereby reducing theinfluence of noise. The configuration of connecting the amplifiers isthe same as that of Embodiment 1.

EMBODIMENT 5

Embodiment 5 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 7 is a top view of Embodiment 5.

In the present embodiment, the wiring constitution is the same asEmbodiment 3 but the connecting positions of amplifiers are differentfrom those of Embodiment 3. Two wirings connected to the same amplifierare arranged on the same position in the wiring direction in the samewiring layer.

With this arrangement, for example, when a signal wiring crosses twowirings connected to the same amplifier, noise from the signal can becancelled.

EMBODIMENT 6

Embodiment 6 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 8 is a top view of Embodiment 6.

Embodiment 4 and Embodiment 5 are combined in the present embodiment andthe same effects of the embodiments 4 and 5 are obtained.

EMBODIMENT 7

Embodiment 7 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 9 is a top view of Embodiment 7.

In the present embodiment, the arrangement of connected amplifiers ischanged from the wiring constitution of Embodiment 2. In thisarrangement, for example, when a method of operating one of twoamplifiers is used, a signal wiring connected to the amplifier not beingoperated has the effect of a shield wiring. Hence, the same effect canbe obtained as the case where a shield wiring is arranged on an adjacentwiring in the same layer.

EMBODIMENT 8

Embodiment 8 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 10 is a top view of Embodiment 8.

Unlike the wiring constitution of Embodiment 1, in the presentembodiment, the arrangement of connected amplifiers is changed and theamplifiers are placed on both ends of a wiring. In this arrangement,like Embodiment 5, two wirings connected to the same amplifier arearranged on the same position in the wiring direction in the same wiringlayer. When a signal wiring crosses two wirings connected to the sameamplifier, noise from the signal can be cancelled.

EMBODIMENT 9

Embodiment 9 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 11 is a top view of Embodiment 9, andFIG. 12 is a sectional view taken along line A1-A2 of FIG. 11. Only thewiring of a second wiring layer on the upper surface side is illustratedin the top view.

First, wirings M11 to M18 are arranged in this order in a first wiringlayer. The wirings M12, M14, M16, and M18 are used as signal lines. Thewirings M11, M13, M15, and M17 arranged between the signal lines M12,M14, M16, and M18 are provided as shield wirings for reducing noise onthe signal lines.

Subsequently, on the first wiring layer, wirings M21 to M28 are arrangedin this order in the second wiring layer. Here, the wirings M21, M23,M25, and M27 are used as signal lines. The wirings M22, M24, M26, andM28 arranged between the signal lines M21, M23, M25, and M27 areprovided as shield wirings for reducing the noise of the signal lines.

In the present embodiment, the signal lines M12, M14, M16, and M18 andthe signal lines M21, M23, M25, and M27 are arranged on differentpositions taken from the top, and the shield wirings are arrangedbetween the signal lines. The shielding effect between the signal linescan be increased as compared with the case where the signal lines arearranged on the same positions taken from the top, thereby furtherreducing the noise of the signal lines. Further, although the shieldwirings are connected to a ground voltage line (GND potential) in thisarrangement, the shield wirings may be connected to a power voltageline.

Embodiment 9 has the following effect: the signal lines are arrangedusing the two wiring layers and the shield wirings are arranged betweenthe signal lines, so that it is possible to reduce a capacitance betweenadjacent wirings, noise between adjacent wirings, and power consumptionwithout reducing the operating speed of a signal. Particularly since thesignal lines of the first wiring layer and the second wiring layer arearranged on different positions taken from the top, achieving a greateffect of shielding noise.

Further, the ground voltage line serving as a shield wiring may be usedas a ground voltage line wired from a power supply or the like.

EMBODIMENT 10

Embodiment 10 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 13 is a top view of Embodiment 10,and FIG. 14 is a sectional view taken along line A1-A2 of FIG. 13. Onlythe wiring of a second wiring layer on the upper surface side isillustrated in the top view.

The arrangement of signal lines is the same as Embodiment 9. Embodiment10 is characterized in that shield wirings are connected to both of aground voltage line and a power voltage line.

Shield wirings M11, M13, M15, and M17 in a first wiring layer areconnected alternately to the ground voltage line and the power voltageline, and shield wirings M22, M24, M26, and M28 in a second wiring layerare connected alternately to the ground voltage line and the powervoltage line. Although the shield wirings are connected alternately tothe ground voltage line and the power voltage line, the order is notalways limited and the most suitable setting can be used in accordancewith the layout.

Embodiment 10 has the same effect as Embodiment 9, and the shieldwirings on both of the ground voltage line and the power voltage lineare used. Thus, the signals can be used as power supply signals of thecircuit.

EMBODIMENT 11

Embodiment 11 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 15 is a top view of Embodiment 11,and FIG. 16 is a sectional view taken along line A1-A2 of FIG. 15. Onlythe wiring of a second wiring layer on the top surface side isillustrated in the top view.

The arrangement of signal lines is the same as Embodiment 9 andEmbodiment 10. Embodiment 11 is characterized in that shield wirings ina first wiring layer are connected to a power voltage line and shieldwirings in the second wiring layer are connected to a ground voltageline.

To be specific, shield wirings M11, M13, M15, and M17 in a first wiringlayer are connected to the power voltage line (VDD potential) and shieldwirings M22, M24, M26, and M28 in a second wiring layer are connected tothe ground voltage line (GND potential).

In this case, the shield wirings in the first wiring layer are used asthe power voltage line and the shield wirings in the second wiring layerare used as the ground voltage line. The reversed arrangement can beused as necessary. The shield wirings in the same wiring layer are usedas the same voltage line, achieving a simple layout.

Embodiment 11 has the same effect as Embodiment 9 and Embodiment 10.Regarding the ground voltage line and the power voltage line, the shieldwirings in the same wiring layer are used as the same voltage line,achieving a simple layout.

EMBODIMENT 12

Embodiment 12 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 17 is a top view of Embodiment 12,FIG. 18 is a sectional view taken along line A1-A2 of FIG. 17, and FIG.19 is a sectional view taken along line B1-B2 of FIG. 17. Only thewiring of a second wiring layer on the top surface side is illustratedin the top view.

In Embodiment 12, a wiring region is broadly divided into two regionsand the two regions of the wiring constitutions in Embodiment 9 areprovided. Further, the wiring of a first wiring layer and the wiring ofthe second wiring layer in the two regions are replaced with each otherand are connected to each other. With this arrangement, each of thewirings is provided both in the first wiring layer and the second wiringlayer, so that a balance of a capacitance and a resistance can beoffered on the wirings and a stable operation can be performed when thewirings are used as bit lines or the like of a memory.

The detailed arrangement will be discussed below. First, in a firstwiring region (cross section along line A1-A2 of FIG. 18), wirings M11to M18 are arranged in this order in the first wiring layer. In thisarrangement, wirings M12, M14, M16, and M18 are used as signal lines.The wirings M11, M13, M15, and M17 arranged between the signal linesM12, M14, M16, and M18 are used as shield wirings for reducing the noiseof the signal lines.

Then, on the first wiring layer, wirings M21 to M28 are arranged in thisorder in the second wiring layer. In this arrangement, the wirings M21,M23, M25, and M27 are used as signal lines. The wirings M22, M24, M26,and M28 arranged between the signal lines M21, M23, M25, and M27 areused as shield wirings for reducing the noise of the signal lines.

Subsequently, a similar wiring constitution is provided in the secondwiring region (cross section along line B1-B2 of FIG. 19). For example,the line M12 is connected to a line M22B, the line M14 is connected to aline M24B, the line M16 is connected to a line M26B, the line M18 isconnected to M28B, the line M21 is connected to a line M11B, the lineM23 is connected to a line M13B, the line M25 is connected to a lineM15B, and the line M27 is connected to a line M17B.

In this arrangement, the shield wirings are connected to a groundvoltage line (GND potential). Of course, the shield wirings may beconnected to a power voltage line, or both of the ground voltage lineand the power voltage line may be used. Although the arrangement isconstituted of the two wiring regions, more wiring regions maybeprovided. When the number of wiring regions is increased, it is possibleto offer a preferred balance of a capacitance and a resistance on eachof the wirings.

Embodiment 12 has the same effect as Embodiment 9. The wiring region isdivided into two or more regions and the wirings of the regions arereplaced with each other before being connected, so that a balance of acapacitance and a resistance on each of the wirings is improved and astable operation can be performed.

EMBODIMENT 13

Embodiment 13 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 20 is a top view of Embodiment 13,and FIG. 21 is a sectional view taken along line A1-A2 of FIG. 20. Onlythe wiring of a second wiring layer on the top surface side isillustrated in the top view.

The arrangement of signal lines is similar to that of Embodiment 9.Embodiment 13 is characterized in that a shield wiring is larger inwidth than a signal line.

Shield wirings M11, M13, M15, and M17 in a first wiring layer and shieldwirings M22, M24, M26, and M28 in a second wiring layer are larger inwidth than signal lines M12, M14, M16, M18, M21, M23, M25, and M27.

Embodiment 13 has the same effect as Embodiment 9. With a larger widthof the shield wiring, the shielding effect can be higher than that ofEmbodiment 9.

Taken from the top, the shield wirings in the first wiring layer and theshield wirings in the second wiring layer do not overlap each other inthe present embodiment. When the shield wirings overlap each other, theshielding effect can be further increased.

EMBODIMENT 14

Embodiment 14 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 22 is a top view of Embodiment 14,and FIG. 23 is a sectional view taken along line A1-A2 of FIG. 22. Onlythe wiring of a second wiring layer on the top surface side isillustrated in the top view.

The arrangement of signal lines in a first wiring layer and the secondwiring layer is similar to that of Embodiment 9. A shield layer M31serving as a third wiring layer is placed between the first wiring layerand the second wiring layer.

Since Embodiment 14 has the shield layer M31 placed as the third wiringlayer, the shielding effect can be increased.

EMBODIMENT 15

Embodiment 15 of the present invention will be discussed below accordingto the accompanying drawings. Regarding wirings arranged as signallines, FIG. 24 is a diagram showing a connecting relationship with senseamplifiers.

Signal lines M12 and M21, signal lines M14 and M23, signal lines M16 andM25, and signal lines M18 and M27 are connected to sense amplifiersSA01, SA02, SA03, and SA04, respectively.

In Embodiment 15, adjacent signal lines of the signal lines in a firstwiring layer and a second wiring layer are connected to the senseamplifiers. When this arrangement is used for bit lines of a memory,adjacent memory cells can be used and thus a stable operation can beobtained for the memory.

EMBODIMENT 16

Embodiment 16 of the present invention will be discussed below accordingto the accompanying drawings. Regarding wirings arranged as signallines, FIG. 25 shows a connecting relationship with sense amplifiers.

Signal lines M21 and M23, signal lines M12 and M14, signal lines M25 andM27, and signal lines M16 and M18 are connected to sense amplifiersSA01, SA02, SA03, and SA04, respectively.

In Embodiment 16, the signal lines connected to the sense amplifier canbe separated away from each other, thereby reducing the influence ofnoise between adjacent signal lines.

EMBODIMENT 17

Embodiment 17 of the present invention will be discussed below accordingto the accompanying drawings. FIG. 26 is a top view of Embodiment 17,and FIG. 27 is a sectional view taken along line A1-A2 of FIG. 26. Onlythe wiring of a second wiring layer on the top surface side isillustrated in the top view.

Signal lines are arranged by combining the arrangement of Embodiment 9and a conventional arrangement which is tightly wired as the lowestwiring layer. The wiring of the lowest layer and the signal lines of afirst wiring layer and a second wiring layer are electrically connectedto each other. This arrangement is used for a memory array using a mainbit line and a sub bit line, so that it is possible to achieve a memoryarray capable of reducing a capacitance between adjacent wirings andnoise between adjacent wirings without lowering the operating speed of asignal.

The above explanation described Embodiments 1 to 17. An arrangementusing these embodiments in parallel is also applicable, which isincluded in the present invention.

Further, the operating method described in Embodiment 7 is alsoapplicable to the other embodiments. With the operation method ofprohibiting half of a plurality of amplifiers from being operated,signal lines connected to amplifiers are used as shield wirings, therebyreducing noise.

Moreover, Embodiment 17 described that the wirings in the lowest layerare arranged in the conventional structure. This arrangement is alsoapplicable to the other embodiments.

Moreover, although the two different wiring layers were discussed in theabove explanation, three or more wiring layers may be arranged.

1. A semiconductor device, in which a first wiring, a second wiring, athird wiring, and a fourth wiring are formed in a first direction in afirst wiring layer, a fifth wiring, a sixth wiring, a seventh wiring,and an eighth wiring are formed in the first direction in a secondwiring layer provided on an upper layer of the first wiring layer, andthe first wiring, the second wiring, the third wiring, the fourthwiring, the fifth wiring, the sixth wiring, the seventh wiring, and theeighth wiring are formed so as to hardly overlap one another taken froma top.
 2. The semiconductor device according to claim 1, wherein thefirst wiring, the second wiring, the third wiring, and the fourth wiringin the first wiring layer are arranged at almost equal intervals.
 3. Thesemiconductor device according to claim 1, wherein regarding the firstwiring, the second wiring, the third wiring, and the fourth wiring inthe first wiring layer, an interval between the first wiring and thesecond wiring and an interval between the third wiring and the fourthwiring are different from each other.
 4. The semiconductor deviceaccording to claim 1, wherein the first wiring, the second wiring, thethird wiring, and the fourth wiring are formed in the first direction inthe first wiring layer, the fifth wiring, the sixth wiring, the seventhwiring, and the eighth wiring are formed in the first direction in thesecond wiring layer provided on the upper layer of the first wiringlayer, a ninth wiring, a tenth wiring, an eleventh wiring, and a twelfthwiring are formed in the first direction in the second wiring layer andare connected to the first wiring, the second wiring, the third wiring,and the fourth wiring, respectively, and a thirteenth wiring, afourteenth wiring, a fifteenth wiring, and a sixteenth wiring are formedin the first direction of the first wiring layer and are connected tothe fifth wiring, the sixth wiring, the seventh wiring, and the eighthwiring, respectively.
 5. The semiconductor device according to claim 1,wherein the first wiring and the fifth wiring, the second wiring and thesixth wiring, the third wiring and the seventh wiring, and the fourthwiring and the eighth wiring are connected to first, second, third, andfourth amplifiers, respectively.
 6. The semiconductor device accordingto claim 1, wherein the first wiring and the second wiring, the thirdwiring and the fourth wiring, the fifth wiring and the sixth wiring, andthe seventh wiring and the eighth wiring are connected to first, second,third, and fourth amplifiers, respectively.
 7. The semiconductor deviceaccording to claim 1, wherein the first wiring and the fifth wiring, thesecond wiring and the sixth wiring, the third wiring and the seventhwiring, and the fourth wiring and the eighth wiring are connected tofirst, second, third, and fourth amplifiers, respectively.
 8. Thesemiconductor device according to claim 1, wherein a first shieldwiring, a second shield wiring, a third shield wiring, and a fourthshield wiring are formed between the first wiring, the second wiring,the third wiring, and the fourth wiring in the first wiring layer, and afifth shield wiring, a sixth shield wiring, a seventh shield wiring, andan eighth shield wiring are formed between the fifth wiring, the sixthwiring, the seventh wiring, and the eighth wiring in the second wiringlayer.
 9. The semiconductor device according to claim 4, wherein a firstshield wiring, a second shield wiring, a third shield wiring, and afourth shield wiring are formed between the first wiring, the secondwiring, the third wiring, and the fourth wiring in the first wiringlayer, a fifth shield wiring, a sixth shield wiring, a seventh shieldwiring, and an eighth shield wiring are formed between the fifth wiring,the sixth wiring, the seventh wiring, and the eighth wiring in thesecond wiring layer, a ninth shield wiring, a tenth shield wiring, aneleventh shield wiring, and a twelfth shield wiring are formed betweenthe ninth wiring, the tenth wiring, the eleventh wiring, and the twelfthwiring in the second wiring layer, and a thirteenth shield wiring, afourteenth shield wiring, a fifteenth shield wiring, and a sixteenthshield wiring are formed between the thirteenth wiring, the fourteenthwiring, the fifteenth wiring, and the sixteenth wiring in the firstwiring layer.
 10. The semiconductor device according to claim 8 or 9,wherein the first to eighth shield wirings are used as ground voltagelines and power voltage lines.
 11. The semiconductor device according toclaim 8 or 9, wherein the shield wirings are larger in width than thewirings.
 12. The semiconductor device according to claim 1 or 8, furthercomprising a third wiring layer between the wirings and shield wiringsformed in the first wiring layer and the wirings and shield wiringsformed in the second wiring layer, wherein the third wiring layer is athird shield wiring.
 13. The semiconductor device according to claim 1or 8, further comprising a wiring layer formed by the fourth wiringlayer under the first wiring layer.